1. Field of the Invention
This invention relates to an apparatus for receiving and decoding a digital signal. More specifically, it concerns a front end for a set top satellite receiver system.
2. Description of the Related Art
Digital broadcast satellite (DBS) communication systems provide reliable long range transmission of information without the need for a pre-existing network of transmission lines and routing switches. However, since the costs entailed in creating a satellite and placing it in orbit are literally astronomical, the economic practicality of these systems depends in large part on widespread use of DBS receiver systems. Consequently containment of the costs while maximizing the performance of DBS receiver systems plays an important role for the emerging DBS technology.
FIG. 1 shows a diagram of portions of a DBS system 100 in operation. A service provider 102 broadcasts a signal by way of a satellite 104 to a user dish 106. In this manner, user dish 106 receives an encoded digital data stream modulated onto a carrier in the Ku-Band (12 GHz). User dish 106 has a down-converter (also referred to as a low-noise block, or LNB) which provides a receive signal 108 to DBS receiver 110. Receive signal 108 is obtained by shifting the frequency of the modulated signal carrier from Ku-Band to the L-Band (1-2 GHz). DBS receiver 110 comprises a front end that demodulates and decodes the digital data stream, and a back end that processes the digital data stream to implement the provided services, e.g. digital cable programming. DBS receiver 110 is colloquially referred to as a set-top box since it is commonly positioned on top of a television set 112 as shown.
In DBS system 100, the digital signal modulation is typically of the binary or quadrature phase shift keying type. The signal passes through the atmosphere and is subjected to various forms of interference. Hence a first issue which must be addressed by the DBS receiver front end is that the received signal is a corrupted version of the transmitted signal. Due to the power restrictions placed on satellite transmission channels, the probability of digital data errors due to signal corruption is substantial. To maximize a signal power to noise power ratio (SNR) of the signal, equalization is used. However, to make satellite communications reliable at high data rates, error correction codes are needed. The error correction coding scheme advocated by the standard "Specifications of the Baseline Modulation/Channel Coding System for Digital Multi-Programme Television by Satellite", European Broadcasting Union, January 1994, is a concatenated coding scheme.
A second issue which must be addressed by the DBS receiver front end is frequency drift. For example, one source of frequency drift is that the carrier frequency of the output signal provided by an economical LNB can drift by .+-.5 MHz with temperature.
FIG. 2 shows one implementation of a DBS receiver front end 200. Front end 200 comprises a tuner 202 and a demodulator/decoder 204. Tuner 202 converts received signal 108 to quadrature baseband signals. Demodulator/decoder 204 converts the quadrature baseband signals to digital form, then performs digital equalization and decoding to produce output data stream 238. As discussed further below, demodulator/decoder 204 also provides feedback signals to tuner 202 for timing and gain control.
Tuner 202 comprises a frequency synthesizer 216 (typically comprising a voltage controlled oscillator), an analog multiplier 206, an intermediate frequency bandpass filter 208, a gain control amplifier 210, an I/Q down converter 212, and a lowpass filter 214. Frequency synthesizer 216 is set by an external microprocessor 236 to be "tuned" to the received signal. The tuned frequency synthesizer provides a signal with a frequency which is offset by a fixed amount (typically 480 MHz) from the frequency of the desired received signal. The fixed amount will be the frequency of a product signal which results when multiplier 206 multiplies the signal from the frequency synthesizer and the received signal.
Multiplier 206 multiplies received signal 108 and the output signal from frequency synthesizer 216 to effectively shift the frequency of received signal 108 to an intermediate frequency (typically 480 MHz) in an intermediate frequency signal. The product signal at the output of multiplier 206 can be expressed as the sum of a desired intermediate frequency signal and other undesired byproduct signals. The product signal is coupled to intermediate frequency bandpass filter 208 which removes the undesired frequency components (and in so doing, removes the undesired byproduct signals) leaving only the intermediate frequency signal.
Output from bandpass filter 208 is coupled to gain control amplifier 210 which regulates the amplitude of the intermediate frequency signal. Gain control amplifier 210 has an adaptive gain which is set to provide a constant-maximum amplitude output signal. The regulation mechanism is a loop filter 234 which operates on a negative feedback signal provided by demodulator/decoder 204. The effect of loop filter 234 is to increase the gain of gain control amplifier 210 when the maximum amplitude of the output signal declines below a target level, and to decrease the gain when the maximum amplitude exceeds a target level.
Output of the gain control amplifier 210 is coupled to I/Q down converter 212 which converts the intermediate frequency signal to quadrature baseband signals. The conversion may take place in a similar fashion to the previous frequency conversion using output from a fixed-frequency oscillator 218, but at baseband two signals are needed. The two baseband signals represent the in-phase (I) and quadrature-phase (Q) components of the intermediate frequency signal. A lowpass filter 214 is employed in the similar fashion to the way baseband filter was used to remove undesired frequency components. In this fashion, tuner 202 converts received signal 108 to quadrature baseband signals.
A third issue which is desirably addressed by the receiver front end is the number of parts required to construct a tuner. Typically, the tuner is constructed using a synthesizer element, an oscillator element, loop filter parts (often discrete components), low pass filter elements, an integrated circuit for the mixer, intermediate frequency bandpass filter, and I/Q downconverter, a metal enclosure (not shown) for RF (radio frequency) shielding, and voltage regulators (not shown) to provide very clean power. A reduction in the part count would advantageously reduce cost and improve reliability.
A fourth issue which must be addressed by the receiver front end is the sensitivity of the tuner to RF noise. Noise control is typically provided by the voltage regulators and metal enclosure. Other noise control features which provide further reduction in RF noise would advantageously improve tuner performance.
Returning to FIG. 2, tuner 202 is followed by demodulator/decoder 204. Demodulator/decoder 204 comprises an analog-to-digital converter (ADC) 220, a decimation block 222, a matched filter 224, a decode logic 226, and a timing, carrier and gain error block 230. ADC 220 converts the quadrature baseband signals into digital form at a sampling rate and sampling phase determined by a signal from a voltage controlled oscillator (VCO) 228. The digital baseband signals are decimated by decimation block 222 (i.e. the sample rate is reduced by dropping a fixed number of samples from each timing interval) to a rate of two samples per symbol interval. Decimation block 224 allows for over-sampling by ADC 220. Over-sampling is the practice of sampling an analog signal at a higher rate than the symbol rate. Use of this practice allows the transfer of some filtering operations from the analog domain to the digital domain. In general, only simple analog filters are practical. For complex filtering operations, digital filters are significantly easier to implement and adjust. By over-sampling and performing the matched filter operation in the digital domain, a substantial implementation complexity reduction is achieved. Furthermore, the use of over-sampling allows relaxed tolerances on the analog filters used in the analog-to-digital conversion process, without significant impairment to the signal-to-noise ratio.
The output of decimation block 222 passes through matched filter 224, which substantially maximizes the signal-to-noise ratio of the digital baseband signals. To accomplish this, the impulse response of matched filter 224 is designed to be the time-reverse of the shape of a signal corresponding to one symbol. Hence, the impulse response is "matched" to the symbol signal. One common symbol signal shape is a square root raised cosine.
The signal provided at the output of matched filter 224 is processed by decode logic 226 to provide error correction and substantially recover the transmitted data stream. This received data stream is then provided as output signal 238. In this manner, demodulator/decoder 204 converts the quadrature baseband signals to digital form, then performs digital equalization and decoding to produce output data stream 238.
The signal provided at the output of matched filter 224 is processed by timing, carrier and gain error block 230 to determine an estimate of error conditions present in the signal. One estimate is for the gain error, and this estimate is passed to loop filter 234, which was described above. A second estimate is for the sampling phase error, and this estimate is passed to loop filter 232. Loop filter 232 operates to regulate the sampling phase and frequency of ADC 220. A third estimate is formed for the carrier frequency offset error. This estimate is periodically sampled by external microprocessor 236 and used to adjust the setting of frequency synthesizer 216. In this manner, demodulator/decoder 204 provides feedback signals to tuner 202 for timing and gain control.
FIG. 3 shows a second implementation of a DBS receiver front end 300. Components which have direct counterparts in front end 200 are numbered identically. Fixed-frequency oscillator 218 has been replaced with an intermediate frequency (IF) VCO 318. IF VCO 318 provides a signal to I/Q down converter 212 which a variable frequency which is regulated by loop filter 319 operating on a feedback signal provided by timing and gain error block 330. This approach allows for continuous monitoring and compensation of a limited amount of frequency drift. Large drifts must still be compensated by intervention of microprocessor 236. This is true because of the effect bandpass filter 208 has on signals which drift out of the range of the pass band.
The two discussed implementations of a DBS receiver front end are previously implemented methods for converting a DBS signal into a received data stream. Improved implementations are desirable. In particular, an implementation which does not require external microprocessor intervention for tracking frequency drift would both reduce cost and improve performance. Also, an implementation of the tuner which converts directly from the received signal to the baseband representation would be more cost effective. To make it feasible to do a direct conversion for DBS, however, a new method for correcting IQ angular error is needed, and a new method for tracking frequency drift is needed. Tighter control must be provided for the lowpass filter since IF filtering is not an option in direct conversion system. Further, any technique which improves the system performance with little or no added cost is desirable.